Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders
نویسندگان
چکیده
منابع مشابه
Design of Synchronous Section-Carry Based Carry Lookahead Adders with Improved Figure of Merit
The section-carry based carry lookahead adder (SCBCLA) architecture was proposed as an efficient alternative to the conventional carry lookahead adder (CCLA) architecture for the physical implementation of computer arithmetic. In previous related works, self-timed SCBCLA architectures and synchronous SCBCLA architectures were realized using standard cells and FPGAs. In this work, we deal with i...
متن کاملComparative Design of 16-Bit Sparse-Tree Rsfq Adder
In this paper, we propse 16-bit sparse tree RSFQ adder (Rapid single flux quantam), kogge-stone adder, carry lookahead adder. In general N-bit adders like Ripple carry adder s(slow adders compare to other adders), and carry lookahead adders(area consuming adders) are used in earlier days. But now the most of industries are using parallel prefix adders because of their advantages compare to kogg...
متن کاملRobust Asynchronous Carry Lookahead Adders
Novel gate level synthesis of robust asynchronous carry lookahead adders based on the notion of section carry is discussed in this paper. For a range of higher order addition operations, the carry lookahead adder is found to exhibit reduced latency than the carry ripple version by 38.6%. However, the latter occupies less area and dissipates less power compared to the former by 37.8% and 17.4% r...
متن کاملA Measurement-Based Form of the Out-of-Place Quantum Carry-Lookahead Adder
We present the design of a quantum carry-lookahead adder using measurement-based quantum computation. The quantum carry-lookahead adder (QCLA) is faster than a quantum ripple-carry adder; QCLA has logarithmic depth while ripple adders have linear depth. Our design is evaluated in terms of number of time steps and the total number of qubits used.
متن کاملLatency Optimized Asynchronous Early Output Ripple Carry Adder based on Delay-Insensitive Dual-Rail Data Encoding
Asynchronous circuits employing delay-insensitive codes for data representation i.e. encoding and following a 4-phase return-to-zero protocol for handshaking are generally robust. Depending upon whether a single delay-insensitive code or multiple delay-insensitive code(s) are used for data encoding, the encoding scheme is called homogeneous or heterogeneous delay-insensitive data encoding. This...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
- Microelectronics Journal
دوره 46 شماره
صفحات -
تاریخ انتشار 2015